Analog-devices ADuC812 Manuel d'utilisateur télécharger pdf (Page 56)

REV. B

–56–

C00208–0–10/01(B)

PRINTED IN U.S.A.

ADuC812

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

52-Lead Plastic Quad Flatpack

(S-52)

TOP VIEW

(PINS DOWN)

PIN 1

4052

2713

0.557 (14.15)

0.537 (13.65)

0.398 (10.11)

0.390 (9.91)

0.014 (0.35)

0.010 (0.25)

0.025 (0.65)

BSC

0.082 (2.09)

0.078 (1.97)

0.012 (0.30)

0.006 (0.15)

0.008 (0.20)

0.006 (0.15)

SEATING

PLANE

0.037 (0.95)

0.026 (0.65)

0.094 (2.39)

0.084 (2.13)

Revision History

Location Page

Data Sheet changed from REV. A to REV. B.

Entire Data Sheet has been revised . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . All

1 2 ... 51 52 53 54 55 56

MicroConverter 1
, Multichannel 1
TABLE OF CONTENTS 2
SPECIFICATIONS 3
ADuC812–SPECIFICATIONS 4
WARNING! 6
PIN FUNCTION DESCRIPTIONS 7
TERMINOLOGY 8
Figure 3. Programming Model 9
YCCA0F1SR0SRVO1FP 10
SPECIAL FUNCTION REGISTERS 11
Figure 6. ADC Result Format 12
1DM0DM1KC0KC1QA0QAC2TCXE 13
ICDAAMDVNOCCVNOCS3SC2SC1SC0SC 14
Driving the A/D Converter 15
Figure 9. Decoupling V 16
ADC DMA Operation 17
Figure 13. DMA Cycle 17
Calibration 18
NONVOLATILE FLASH MEMORY 18
Flash Memory Overview 18
Programming 19
Configuration 19
Using the D/A Converter 22
OUTPUT VOLTAGE – V 23
WATCHDOG TIMER 24
—PMCIMSP2PT1PT0PTFSPNEMSP 25
(CPHA = 1) 27
(CPHA = 0) 27
Parallel I/O Ports 0–3 29
Timers/Counters 29
Register 30
TH0 and TL0 31
TH1 and TL1 31
Mode 0 (13-Bit Timer/Counter) 32
Mode 1 (16-Bit Timer/Counter) 32
TH2 and TL2 33
RCAP2H and RCAP2L 33
Timer/Counter Operation Modes 34
16-Bit Autoreload Mode 34
16-Bit Capture Mode 34
UART SERIAL INTERFACE 35
SCON UART Serial Port Control 35
Timer 1 Generated Baud Rates 37
Timer 2 Generated Baud Rates 37
INTERRUPT SYSTEM 38
IE: Interrupt Enable Register 38
—————— IMSPEISE 39
Clock Oscillator 40
External Memory Interface 40
Power-On Reset Operation 41
Power Supplies 41
Power Consumption 42
Table XXVIII. Typical I 42
of Core and Peripherals 42
OTHER HARDWARE CONSIDERATIONS 44
Embedded Serial Port Debugger 44
TIMING SPECIFICATIONS 46
Figure 55. I 51
C-Compatible Interface Timing 51
Revision History 56

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