Analog-devices ADSP-2186 Manuel d'utilisateur télécharger pdf (Page 19)

ADSP-2186

REV. 0

–19–

Parameter Min Max Unit

Bus Request/Grant

Timing Requirements:

BR Hold after CLKOUT High

0.25 t

+ 2 ns

BR Setup before CLKOUT Low

0.25 t

+ 17 ns

Switching Characteristics:

CLKOUT High to xMS, RD, WR Disable 0.25 t

+ 10 ns

SDB

xMS, RD, WR Disable to BG Low 0 ns

BG High to xMS, RD, WR Enable 0 ns

SEC

xMS, RD, WR Enable to CLKOUT High 0.25 t

– 7 ns

SDBH

xMS, RD, WR Disable to BGH Low

0ns

SEH

BGH High to xMS, RD, WR Enable

0ns

NOTES

xMS = PMS, DMS, CMS, IOMS, BMS.

BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on

the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.

BGH is asserted when the bus is granted and the processor requires control of the bus to continue.

CLKOUT

SDB

SEC

SDBH

SEH

CLKOUT

PMS, DMS

BMS, RD

BGH

Figure 16. Bus Request–Bus Grant

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 31 32

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Analog-devices ADSP-2186 Manuel d'utilisateur Page 19

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