Analog Devices AD9843A Manuel d'utilisateur

REV. 0Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsu

AD9843A–10–REV. 0SERIAL INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTIONTable I. Internal Register MapRegister Address Data BitsName A0 A1 A2 D0 D1

AD9843A–11–REV. 0Table II. Operation Register Contents (Default Value x000)Optical Black Clamp Reset Power-Down Modes Channel Selection D10 D9 D8 D7 D

AD9843A–12–REV. 02dB TO 36dBCLPDMCCDIN10DIGITALFILTERINGCLPOBDC RESTOREINPUT OFFSETCLAMPOPTICAL BLACKCLAMP0 TO 64 LSB0.1FDOUT10-BITADCVGA8-BITDAC8VGA

AD9843A–13–REV. 0together with CLPOB or separately. The CLPDM pulse shouldbe a minimum of four pixels wide.Variable Gain AmplifierThe VGA stage provid

AD9843A–14–REV. 0Table VIII. VGA Gain Register Used for AUX2-ModeMSB LSBD10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Gain (dB)X0 XXXXXXXXX0.010000000000.0••••••1

AD9843A–15–REV. 0APPLICATIONS INFORMATIONThe AD9843A is a complete Analog Front End (AFE) productfor digital still camera and camcorder applications.

–16–C02194–0–10/00 (rev. 0)PRINTED IN U.S.A.AD9843AREV. 0OUTLINE DIMENSIONSDimensions shown in inches and (mm).48-Lead LQFP(ST-48)TOP VIEW(PINS DOWN)1

–2–REV. 0AD9843A–SPECIFICATIONSGENERAL SPECIFICATIONSParameter Min Typ Max UnitTEMPERATURE RANGEOperating –20 +85 °CStorage –65 +150 °CPOWER SUPPLY VO

–3–REV. 0AD9843AParameter Min Typ Max Unit NotesPOWER CONSUMPTION 78 mW See TPC 1 for Power CurvesMAXIMUM CLOCK RATE 20 MHzCDSAllowable CCD Reset Tran

–4–REV. 0AD9843A–SPECIFICATIONSAUX1-MODE SPECIFICATIONSParameter Min Typ Max UnitPOWER CONSUMPTION 60 mWMAXIMUM CLOCK RATE 20 MHzINPUT BUFFERGain 0dBM

AD9843A–5–REV. 0TIMING SPECIFICATIONSParameter Symbol Min Typ Max UnitSAMPLE CLOCKSDATACLK, SHP, SHD Clock Period tCONV48 50 nsDATACLK High/Low Pulsew

AD9843A–6–REV. 0PIN CONFIGURATION36353433323130292827262513 14 15 16 17 18 19 20 21 22 23 2412345678910111248 47 46 45 44 39 38 3743 42 41 40PIN 1IDEN

AD9843A–7–REV. 0DEFINITIONS OF SPECIFICATIONSDIFFERENTIAL NONLINEARITY (DNL)An ideal ADC exhibits code transitions that are exactly 1 LSBapart. DNL is

AD9843A–8–REV. 0SAMPLE RATE – MHz100704052010POWER DISSIPATION – mW5060809015VDD = 3.3VVDD = 3.0VVDD = 2.7VTPC 1. Power vs. Sample Rate01000400200 600

AD9843A–9–REV. 0CCD-MODE AND AUX-MODE TIMINGN–10 N–9N–8N–1NN N+1 N+2 N+9 N+10tIDtIDtS1tS2tCPtINHtODtHNOTES:1. RECOMMENDED PLACEMENT FOR DATACLK RISIN